1. Field of the Invention
The present invention relates generally to a frequency synthesizer, and more particularly, to a method for using the architecture of digital process frequency loop (DPFL) with a processor and a DAC (Digital to Analog Converter) to construct an electronic frequency synthesizer.
2. The Prior Arts
The frequency synthesizer has been widely used to generate the target frequency corresponding to system requirement in many electronic applications for years. One of the most common frequency synthesizers is the PLL frequency synthesizer, in which the PLL includes a phase detector and a charge pump or a low pass filter. As well known, the PLL frequency synthesizer in the prior arts was invented in the 1930s.
With reference to FIG. 1, the block diagram of the PLL frequency synthesizer shows that the synthesizer includes a frequency divider 1, a phase detector 2, a low pass filter/charge pump 3, a voltage control oscillator (VCO) 4 and an output frequency divider 5. The synthesizer has a reference frequency fREF as an input signal, which is quite stable. The characteristic of the VCO 4 is that the output frequency fO of the VCO will change when the input voltage of the VCO changes, as shown in FIG. 4.
The reference frequency with high stability is fed straight to one input of the phase detector 2 or fed through the frequency divider 1 that divides down the reference frequency before it feeds to the input of the phase detector 2. Another frequency that is generated from the VCO 4 of the frequency synthesizer also is divided down by the output frequency divider 5 and feeds into another input of the phase detector 2.
The function of the phase detector 2 is to generate a voltage in proportion to the amount of the phase difference between the two inputs of the phase detector 2, when the reference frequency is leading or lagging. The generated voltage then passes through a low pass filter/charge pump 3 to steer the VCO 4 to a frequency that will make the two input signals in phase at the input of the phase detector 2. As a result, the output frequency of the VCO 4 is said to lock on to the reference frequency. The phase detector 2 has no output voltage when the two signals are in phase. It relies on the charge pump 3 to maintain the input voltage of the VCO 4. The charge pump 3 will lose its voltage because of the leakage current that causes the VCO 4 to change its frequency until the phase difference is large enough for the phase detector 3 to realize the difference and start to provide the corresponding voltage to the charge pump 3 to bring it back to the targeted frequency.
There are two drawbacks in the traditional PLL frequency synthesizer. Firstly, the PLL frequency synthesizer has two variables to deal with, including the frequency and the phase. As well known, the phase difference obtained by the phase detector does not have any information about the frequency or vice versa. Secondly, the VCO starts to react to the voltage when the charge pump is charging. The output frequency divider is continuously counting. Some unwanted frequencies will be unwontedly captured. These unwontedly captured frequencies become smaller and smaller as the output frequency gets closer to the final frequency. It will take several tries to lock.